Interoperable Toolbox of Run Time Reconfigurable Digital Signal Processing Modules

Navy SBIR 22.2 - Topic N222-113
ONR - Office of Naval Research
Opens: May 18, 2022 - Closes: June 15, 2022 (12:00pm est)

N222-113 TITLE: Interoperable Toolbox of Run Time Reconfigurable Digital Signal Processing Modules

OUSD (R&E) MODERNIZATION PRIORITY: 5G; Microelectronics;Networked C3

TECHNOLOGY AREA(S): Electronics; Information Systems; Sensors

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop a Situational Awareness (SA) system that combines all classes of commercial off-the-shelf (COTS) digital processors and record capability.

DESCRIPTION: SA systems strongly need the ability to quickly sense and adapt their priorities to changes in the battle space environment which are expected to evolve much more quickly in the future than in the past. Both the mix of signals present and the details of the waveforms utilized are expected to change. Both because understanding new signals is more processor intense than standard signals and cost pressures favor minimal processing power, it is critical to optimize processor utility if the user is not to be surprised by unrecognized threats. This SBIR topic focuses on the design of the processing control system. It assumes that all 3 types of COTS Digital Signal Processing (DSP) modules will be present and that the GOTS processing modules will have different computational efficiencies and latencies on each kind of hardware. Independent of the system’s size scale and hardware (HW) blend, a facile way of altering the allocation of processing resources among the different signals of interest (SOI) as the situation evolves is needed. In particular, the Navy seeks development of a cost function for use in AI-based system control algorithms which reflects both the effectiveness of a particular processor in addressing a specific class of SOI and the current importance of that SOI to the outcome of the battle. The latency and energy costs of changing the HW class used needs to be included and minimized wherever possible. Moreover, within every processing module for each class of SOI, the ability to respond to an interrupt signal and reconfigure its processing for a new SOI is essential. A way to quantify each module’s degree of completion of a given processing task and alternatives to simple dropping all partially completed results are desirable to invent.

Proposals should include tasks to Architect and demonstrate a Situational Awareness system which combines all classes of COTS digital processors and record capability. Include branching routing and fan-out that is conditional and based on the content of signal data, interrupt driven partial reconfiguration (alteration of the algorithmic instructions as well as data), and during operation updates to signal processing parameters. Develop one or more cost functions for the optimization of the realized processor loading that incorporates the operational priority of each class of signal being worked, the degree of completion of processing likely achieved by a given allocation of processor resources, and a measure of the operational cost of all the signals and tasks ignored for lack of sufficient system processing capacity.

The planned system should in all cases be compatible with scaling to handle 1,000 simultaneous signals received by a multi-bit 20 GHz Nyquist band receiver front end.

• At the threshold level of performance and in actually planned demonstrations, focus on a system limited in total power to 5 KW and constrained to a processor volume of 18x18x26 inches. If active cooling fits within the energy budget, it may be considered.

• At the objective level of performance, design a 100 KW system and define all alterations necessary to complete the processing if 50% of the information comes from the partially digested results delivered from off-board systems (versus response to new real time information).

Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by DoD 5220.22-M, National Industrial Security Program Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and ONR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material IAW DoD 5220.22-M during the advanced phases of this contract.

PHASE I: During the base period, elaborate the proposed architectural structure into a notional 3 class of processor system design at the threshold level of complexity and develop the requested adaptive performance-based cost function for it. Determine a strategy for handling reassignment of a SOI between the HW classes. Determine technical risks. If the Phase I option is exercised, perform validation studies of the modules designed for scaling system capacity on the proposed example set of signals. Prepare and provide a Phase II plan.

PHASE II: Develop and demonstrate a prototype product threshold scale adaptive processing system during the base award. Develop a plan for an objective scale system. Retire one or more technical risk items. If the Phase II option is exercised, demonstrate the scale system the cost-share sponsor wants to realize and experimentally test.

It is probable that the work under this effort will be classified under Phase II (see Description section for details).

PHASE III DUAL USE APPLICATIONS: Perform field validation of the delivered hardware. Test its performance advantages. The cost function could be used to design optimal processors for specific signal systems.


  1. Garg, Vijay K. "Chapter 23 - Fourth Generation Systems and New Wireless Technologies." Wireless Communications & Networking, 2007.
  2. "What is Software Defined Radio."
  3. "FPGAs for DSP and Software-Defined Radio." UCLA Extension, Engineering Short Courses.
  4. Ferguson, John D.; Witkowski, Peter; Kirschner, William and Bryant, Daniel. "Deepwave Digital: AI Enabled GPU Receiver for a Critical 5G Sensor." Nvidia Corporation and Deepwave Digital.

KEYWORDS: Field Programmable Gate Arrays; Graphical Processing Units; central processing units; rates for data loading; energy efficiency of processing; processing latency; cost functions in Artificial Intelligence/Machine Learning; router architectures


The Navy Topic above is an "unofficial" copy from the overall DoD 22.2 SBIR BAA. Please see the official DoD Topic website at for any updates.

The DoD issued its 22.2 SBIR BAA pre-release on April 20, 2022, which opens to receive proposals on May 18, 2022, and closes June 15, 2022 (12:00pm est).

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