N152-096        TITLE:  Miniaturized, Fault Tolerant Decentralized Mission Processing Architecture for Next Generation Rotorcraft Avionics Environment

TECHNOLOGY AREAS:  Air Platform, Information Systems, Electronics

ACQUISITION PROGRAM:   PMA 275 V22 Osprey Program and PMA 276 H-1 Helicopter Program

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals

(FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. 

OBJECTIVE:  Develop a decentralized mission processing architecture/system capable of distributed processing amongst multiple fully capable mission computer nodes with a higher degree of fault tolerance/reliability allowing for at least a designation of Mission Critical with an objective of Flight Critical level of reliability operating in conformance with the Future Airborne Computing Environment (FACE) standard.

DESCRIPTION:  Most avionics systems for rotorcraft currently rely on a federated mission

computer/processing architecture which centralizes the aggregation of data for processing and subsequent Human Machine Interface (HMI)/subsystem transmission. Current Rotocraft Federated architecture habitually claims redundancy by having a secondary processing computer that is either fully capable, or has a reduced situational awareness (S/A) capability giving the operators a 'fly home' mode upon failure of the primary processing unit. This architecture has resulted in development of high cost mission computers, $200K-$400K/unit, requiring multi-million dollar investments by the government. This centralized processing system worked in the past as power usage was lower; however, newer systems using commercial off the shelf (COTs)/government off the shelf (GOTs) processing boards in a 3U and 6U format are high speed/high power creating the need for heat rejection >200W for a relatively small surface area which is expected to increase as more video intensive processing is introduced with the Digital Terrain Elevation Data (DTED) II/III based tracking and digital map systems. As part of this effort, an evaluation of the integration of COTs/GOTs systems vs custom design needs to be investigated to optimize the processing profile. This system should be fault tolerant, capable of losing up to 50% of the processing nodes while maintaining full situational awareness (S/A) across 4 Extended Graphics Array/High Definition (XGA/HD) (720 and 1080p) displays, processing map, digital video and A/C sensors. Additionally it should have a singular nodal processing system of at least 3 nodes with a documented expandability limit, a unit cost 20% or less of existing mission computers which cost $200,000 - $300,000. Another systems integration based point to consider is that the majority of aircraft avionics systems are designed for a 1553B daisy chain architecture for digital data transfer. New, higher speed systems rely more on a hub/spoke architecture with designated relay points (i.e., Ethernet) which drive physical integration issues based on the eight (8) wires necessary for connection between each node vs two (2) wires for legacy wired communications systems, i.e., 1553 and serial. Modular Open Systems Architecture (MOSA) and the Future Airborne Computing Environment (FACE) will be required for the majority of Avionics components in the future. While a MOSA computing environment should be achievable, there has been some debate about the ability to utilize an abstraction layer and maintain a true Real-Time processing environment. This issue should be addressed in the design of this system, identifying roadblocks to full FACE conformance and potential mitigations. This architecture could be utilized as a host architecture/framework for next generation Jet Engine controls, serving as the enabling functions for a dynamic distributed controls system if a the flight critical level of reliability and signal integrity is achieved during this effort. 

PHASE I:  Determine the technical feasibility of distributed avionics architecture, identifying any technological breakthroughs necessary to meet the high-uptime system requirements and distributed processing stability. 

PHASE II:  Produce a prototype mission processing architecture validating the proposed design from Phase I that is capable of being certified for flight. The actual certification process need not be completed for this phase but a high degree of confidence that the hardware qualification required for a Safety of Flight or Mission Critical System will be achieved. Demonstrate full functionality, automatically without operator intervention, when one of the nodes is disabled. 

PHASE III:  Produce a set of Production Representative Units PRU's (pre Low Rate Initial Production LRIP units) for retrofit integration into an AH-1Z utilizing the existing monolithic software running on an existing rotorcraft platform demonstrating the ability to process the existing software in at least three separate, fully redundant nodes. Commercial applications, such as the automotive and manufacturing industry, will also be continued to be developed. 

REFERENCES:  

1.                Bieber, P., Boniol, F. (May 2012). New Challenges for Future Avionic Architectures, Aerospacelab Journal Issue 4, AL04-11.

2.                Kim J., Yoon M. (July 2014). Integrated Modular Avionics (IMA) Partition Scheduling with ConflictFree I/O for Multicore Avionics Systems, 2014 IEEE 38th Annual COMPSAC.

3.                Jakovljevic, M. (Oct 2013). 2nd generation IMA: Extended virtualization capabilities for optimized architectures, 2013 IEEE/AIAA 32nd DASC.

KEYWORDS:  Avionics; Mission Computer; Mission Processing; Architecture; engine controller; RTOS

** TOPIC AUTHOR (TPOC) **

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