Three-Dimensional (3D) Interconnect Technology to Improve Size, Weight, Power, and Cost (SWAP-C) of Current and Future Electronic Systems
Navy SBIR 2015.3 - Topic N153-130
NSMA - Mr. John Keiran - john.keiran@navy.mil
Opens: September 28, 2015 - Closes: October 28, 2015

N153-130 TITLE: Three-Dimensional (3D) Interconnect Technology to Improve Size, Weight, Power, and Cost (SWAP-C) of Current and Future Electronic Systems

TECHNOLOGY AREA(S): Electronics

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the solicitation. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Fabricate and demonstrate three-dimensional (3D) interconnect technology between heterogeneous wafers in an effort to significantly reduce the Size, Weight, Power, and Cost (SWAP-C) of current and future systems.

DESCRIPTION: As 2.5D/3D technology starts to reach mainstream production in the electronics industry, opportunities exist to develop this technology for use in many defense applications. Dense levels of integration at the wafer interconnect level and potentially the device level would significantly reduce the SWaP (Size, Weight and Power) of current and future systems. Oftentimes, in both military and commercial systems, requirements exist for a non-standard reticle size or interconnect technology to meet custom application needs. This solicitation will explore the ability of the current industry wafer fabrication base to create custom wafer stacks with a large number of interconnects in the vertical (via) and horizontal (trace) dimensions across an entire wafer and wafer stack.

It is desired to fabricate, at the end of Phase II, a five layer wafer stack that consists of wafers at least 150mm in diameter, with each wafer containing a minimum of 500,000 interconnects to the wafer above and/or below it. The topmost and bottommost wafers are excluded from this requirement and need only demonstrate interconnects to the wafer above or below. The interconnect density should be evenly spread across, to the extent possible, the entire 150mm wafer stack. Current IC technology has high interconnect density in the chip itself but interconnect technology to the circuitry above or below, for example in a wafer stack, is typically much less.

A methodology to test every connection from a DC perspective is required to obtain yield data. The wafer stack must contain at least one Silicon wafer, and may contain more than one, but it is ultimately desired for the wafer stack to contain other substrate materials. Sapphire, Gallium Arsenide, Silicon Dioxide, Gallium Nitride (GaN), and Indium Phosphide are potential candidates, and may be integrated with other materials, for example GaN on diamond. Other material or combinations thereof may be submitted for consideration. The bonding and interconnect methodology is not defined and up to the performer to determine. The performer must show that any bonding techniques do not cause detrimental effects, for example too high of a coefficient of thermal expansion (CTE) mismatch causing structural damage, to any potential active devices contained within any of the candidate substrates. The desired interconnect metal is copper to maintain maximum compatibility with current industry fabrication techniques, however other interconnect metallurgy will be considered if appropriate. If required, a handle wafer may be counted as one of the mandatory wafers.

PHASE I: Phase I is a technology feasibility phase and will determine the best fabrication processes and methodologies to design, fabricate, and test a wafer stack meeting previously discussed requirements. A report detailing the outcome of Phase I is required. The report should describe the approach to be used to demonstrate 3D interconnect between wafers if awarded the Phase II effort.

PHASE II: Phase II will require the successful bonding of at least three wafers, one of which must be Silicon and one of which must be another dissimilar material, having at least one million measurable connections between the wafers, with greater than 99% yield.

PHASE III DUAL USE APPLICATIONS: If Phase II is successful, the small business will provide support in transitioning the technology for Navy use, with a focus on scaling manufacturing capabilities and commercialization plans.

REFERENCES:

1. Betty Prince (ed), 2014, "3D Stacking of RAM-Processor Chips Using TSV, in Vertical 3D Memory Technologies", John Wiley & Sons Ltd, Chichester, United Kingdom, DOI: 10.1002/9781118760475.ch06

2. Philip Garrou, Mitsumasa Koyanagi, and Peter Ramm, 2014, "Handbook of 3D Integration", Wiley-VCH, Weinheim, Germany, ISBN:978-3-527-33466-7

KEYWORDS: Three-Dimensional (3D); Wafer scale; Three-Dimensional (3D) Interconnect; Wafer stacking; Vias; Yield; Heterogeneous

TPOC-1: Brian Higgins
Phone: 202-284-2256
Email: brian.c.higgins@navy.mil

TPOC-2: Greg Rash
Phone: 760-939-7133
Email: gregory.rash@navy.mil

Questions may also be submitted through DoD SBIR/STTR SITIS website.

** TOPIC AUTHOR (TPOC) **
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