Drift Step Recovery Diode (DSRD) for Wideband (WB) and Ultra-Wideband (UWB) Pulse Generation
Navy SBIR 2018.2 - Topic N182-130
ONR - Ms. Lore-Anne Ponirakis - loreanne.ponirakis@navy.mil
Opens: May 22, 2018 - Closes: June 20, 2018 (8:00 PM ET)

N182-130

TITLE: Drift Step Recovery Diode (DSRD) for Wideband (WB) and Ultra-Wideband (UWB) Pulse Generation

 

TECHNOLOGY AREA(S): Battlespace, Electronics

ACQUISITION PROGRAM: ONR Code 352: High Power Microwave (HPM) Basic Research

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop a drift step recovery diode (DSRD) component for High Power Microwave (HPM) technology applications to improve variance in waveform shape, through pulse width and rise time, and pulse repetition frequency (PRF).

DESCRIPTION: Wideband (WB) and Ultra-Wideband (UWB) High Power Microwave (HPM) source performance parameters can be described in terms of source power in peak electric potential, pulse repetition rate, unmodulated pulse width, and pulse rise time. When comparing pulse compression techniques, it is apparent that the densities of energy stored in an inductor is higher than in a capacitor, and thus the pulsed voltage generated during a short time at a load may be many times higher than the voltage at which the energy has been stored [Ref 1]. HPM sources utilizing inductive storage techniques to generate high peak electric fields are typically limited in their performance by the nanosecond opening switches [Ref 1]. In the mid-1980s the usual process of high-power silicon diode recovery after pumping with electron-hole plasma by forward current pulse, under special conditions, proceeds for units of nanoseconds. This process was used as a physical basis for the design of DSRDs, a very high-power and relatively inexpensive semiconductor opening switch with a long (practically unlimited) operating life and high repetition rate, limited mainly by cooling system capability [Ref 2]. Manufacture of the DSRD typically requires deep diffusion to form thick p+ and n+ layers of a p+nn+ structure, where thick is considered to be on the order of 90um [Ref 1].

To create better performing DSRDs, it is essential to consider the reverse recovery time (trr), peak blocking voltage, and peak current carrying capabilities of the semiconductor. The trr is comprised of two components: the store charge depletion time (ts) and the switching time (tr). After the stored charge is depleted, the diode switches from low impedance to high impedance in the switching time. The switching time is controlled primarily by the recombination of minority carriers in the crystal material. If tr is much less than ts, the transition is characterized as abrupt. Ideally the diode switches in zero time [Ref 3].

In recent applications DSRDs have been used in higher voltage situations where more pumping current and blocking voltage is required. These voltages can be on the order of 50-150kV+ and currents >10kA, which have been achieved through by building arrays of individual DSRDs. The advantage is that higher voltages and currents can be implemented; the disadvantage is the internal inductance, capacitance, and resistance of the DSRD stacks becoming large and creating unwanted effects on the circuit.

The USN requires DSRDs with the following characteristics:

Single DSRD Operating Requirements
• Operating voltage: >400V with FWHM <1 ns or >600V with FWHM <5 ns
• Peak Repetitive Operating current: 1 kA
• Pulse repetition frequency: 500 kHz (1 MHz desired)
• Switching time: <1 ns
• Differential voltage (-dV/dt): 2000 V/ns
• Stackable design with low loss
• Form factor: circular diameter of 0.25”-0.8”

In addition to this, at these power levels thermal management can become an issue. Respondents should include a plan to evaluate and mitigate heat generation. Initial design points including doping profiles and Si wafer properties can be provided.

PHASE I: Single DSRD Development

Develop DSRDs for nanosecond or faster pulsed HPM sources. The required high voltage DSRD diodes must have the specific electrical and performance characteristics previously listed as well as be in the smallest form factor possible to fit within the operational footprint. The two types of DSRDs considered will be those producing a sub-ns FWHM pulse of approximately 400V with a single device into a 50 O load, and those producing FWHM of <5ns pulse of approximately 600V into a 50 O load, with both DSRDs operating in pulse generating mode with ultra-fast opening switch. Device metrics that must be met for the success of this SBIR effort include the near instantaneous switching times as observed from reverse recovery time (trr) testing (time from low impedance to a high impedance state), carrier lifetime evaluation for high repetition repeatability (time from high impedance back to a low impedance state), voltage breakdown of approximately 400-600V per DSRD, and round profile with ability to stack with low impedance. Additionally in Phase I, develop a plan for Phase II to array the devices to increase voltage and current to levels indicated in the Phase II requirements.

PHASE II: DSRD Array Development

Demonstrate stacked DSRD arrays capable of 5-10 kV breakdown, 0.25” diameter, FWHM pulses in the range 1-10 ns or 50-500 ps into 50 O loads capable of operating at PRF >500 kHz. Development will include device fabrication, dicing, stacking, and passivation techniques with the goal of reducing impedance and capacitance in order to improve voltage standoff, peak current, and trr.

PHASE III DUAL USE APPLICATIONS: While still seeking improvements to the device performance, develop manufacturing methods to improve component yield, production time, and component cost. Criteria for the DSRD performance in Phase III are still dependent on the parameters of Phase II. The new criteria for this phase include the time and cost to produce the DSRD wafer and stacked wafer components.

DSRDs have been used in the kicker systems for the acceleration of a particle [Ref 4]. There is potential for solid-state, high-voltage, nanosecond DSRD sources to be used to in a next-generation type of ignition system for gasoline combustion engines called “plasma-assisted combustion technology”, which both improves engine performance by increasing lean burn flammability and reduces emissions by applying non-equilibrium plasma to gasoline [Ref 5].

REFERENCES:

1. Mesyats, G. A. Pulsed Power. New York, NY: Springer Science+Business Media, Inc. 2005.

2. Grekhov, I.V., Efanov, M., Kardo-Sysoev, A.F., and Shenderey, S.V. “Power Drift Step Recovery Diode.” Solid State El., vol. 28, pp. 597–599, 1985. https://www.sciencedirect.com/science/article/pii/0038110185901303

3. Focia, R., Schamiloglu, R., Fleddermann, C., Nunnally, W., and Gaudet, J. “Ultrafast High Power Switching Diodes.”  Pulsed Power Conference, 1995. Digest of Technical Papers., Tenth IEEE International, August 1995. http://ieeexplore.ieee.org/document/596804/

4. Arntz, F., Kardo-Sysoev, F., and Krasnykh, A. “SLIM, Short-pulse Technology for High Gradient Induction Accelerators.”  Pulsed Power Conference, 2009 IET European, SLAC-PUB-13477, December 2008. http://ieeexplore.ieee.org/document/5332164/

5. Nakamura, K., Akiyama, H., and Sakugawa, T. “Plasma-Assisted Combustion Technology using Nanosecond Pulsed Power.”  Power Modulator and High Voltage Conference (IPMHVC), 2016 IEEE International (IEEE). http://ieeexplore.ieee.org/document/8012880/

KEYWORDS: Drift Step Recovery Diode; DSRD; Silicon Opening Switch; SOS; High Power Radio Frequency; HPRF; Pulse Repetition Frequency; PRF; Small Boat Attack; Small UAV UAS Attack; Counter Swarm; High Power Microwave, HPM; Solid State; Ultra-Wideband; UWB

 

** TOPIC NOTICE **

These Navy Topics are part of the overall DoD 2018.2 SBIR BAA. The DoD issued its 2018.2 BAA SBIR pre-release on April 20, 2018, which opens to receive proposals on May 22, 2018, and closes June 20, 2018 at 8:00 PM ET.

Between April 20, 2018 and May 21, 2018 you may talk directly with the Topic Authors (TPOC) to ask technical questions about the topics. During these dates, their contact information is listed above. For reasons of competitive fairness, direct communication between proposers and topic authors is not allowed starting May 22, 2018
when DoD begins accepting proposals for this BAA.
However, until June 6, 2018, proposers may still submit written questions about solicitation topics through the DoD's SBIR/STTR Interactive Topic Information System (SITIS), in which the questioner and respondent remain anonymous and all questions and answers are posted electronically for general viewing until the solicitation closes. All proposers are advised to monitor SITIS during the Open BAA period for questions and answers and other significant information relevant to their SBIR/STTR topics of interest.

Topics Search Engine: Visit the DoD Topic Search Tool at sbir.defensebusiness.org/topics/ to find topics by keyword across all DoD Components participating in this BAA.

Proposal Submission: All SBIR/STTR Proposals must be submitted electronically through the DoD SBIR/STTR Electronic Submission Website, as described in the Proposal Preparation and Submission of Proposal sections of the program Announcement.

Help: If you have general questions about DoD SBIR program, please contact the DoD SBIR Help Desk at 800-348-0787 or via email at sbirhelp@bytecubed.com