Forensic Memory for Self-Cued, Data-Thinning Receivers

Navy SBIR 22.1 - Topic N221-071
ONR - Office of Naval Research
Opens: January 12, 2022 - Closes: February 10, 2022 (12:00pm est)

N221-071 TITLE: Forensic Memory for Self-Cued, Data-Thinning Receivers

OUSD (R&E) MODERNIZATION PRIORITY: 5G;Microelectronics;Networked C3

TECHNOLOGY AREA(S): Electronics;Information Systems;Sensors

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Demonstrate a digitally-based, forensic First-In, First-Out (FIFO) memory technology. Then, at a threshold level of performance, develop methods to locate within the exiting flowing data the specific subset corresponding to cued time/frequency segments and deliver them into a back-end data fusion processor. At the objective level of performance, demonstrate successful sub-nanosecond re-aggregation of common time of arrival events from multiple disjoint frequency subchannels. Ensure memory concepts are compatible with data rates scaling to multi-bit, 40 GSamples per second or more and provide time offsets of 100 microseconds or more per modular copy. Consider desirable low power operation and low acquisition cost.

DESCRIPTION: The increasing military use of highly adaptive transmit signals mean that U.S. electronic support receivers need to respond to unpredicted single pulses. Hence they need to include the ability to self-cue on signals within their input bandwidth that just appeared in the spectrum and match the current criteria of signals of interest. Unfortunately, by the time the new signal is detected and categorized as of interest, its occurrence is often over. Hence unless the entire spectrum has been recorded, there is then no possibility to study that first occurrence in greater detail, especially if the data was consumed in the event detection process. In particular, there is no way to look just before the pulseís onset to see whether there is a characteristic precursor signal. What is needed is a forensic memory, a way to look back in time and access the entire signal after it is declared of interest. To be practical, this memory ought not to require massive RAM memories, cost, or power consumption to operate and should produce a long enough delay to allow digital processors working in parallel on multiple, identical quality copies of the entire spectrum data sufficient time to provide cueing information for all the currently prioritized events of interest happening in the given time window.

Today such memories do exist where a power divider sends an analog copy of the signal into passive optical fiber, while the rest of the received energy feeds a receiver that detects the signals of interest (SOI). This architecture can work but requires substantial distortion--inducing amplification to achieve long enough delays and often an entire digitization front end per SOI output. For full spectrum, many simultaneous signal systems, the cost and complexity/volume of the resulting redundant hardware and control networks becomes prohibitive.

Future ES systems need to surveil over 20 GHz of instantaneous bandwidth and respond to a variable but potentially large number of simultaneous signals in all frequency channels monitored, without having the rigidity of designating which frequency channel a given processor addresses. The Analog to Digital Converters required increasingly exist. What is missing is a way to capture and hold temporarily the digital representation of the entire spectrum and then in real time fan out perfect copies to a scalable set of following digital processors that have been cued as to the time, as well as frequency, of the individual SOI they are to process. The ability to aggregate information derived from disjointed frequency channels is also required. A permanently-record-everything approach allows deep inspection of what happened, but normally only after the immediate operational value of the information has expired. It also requires prodigious volumes of memory that consumes energy and volume and manpower to keep changing storage devices. Real-time systems must have a way to reduce the volume of data being extensively processed to what processing the system can accomplish in real time. Therein copies of the same digital data as used for event detection/cue preparation need to sent to the data thinning circuits. Memory delays sufficiently long for the cues to be prepared and prioritized for further attention are required. Ideally the temporary digital data storage mechanism should not depend on the digital data sample rate. Here the first demonstration ought to consider use of the COTS 100 GbE fiber data links commonly used in server farms. Other solutions suitable for > 20 GSps multi-bit analog to digital converters (ADC) will be considered if the proposals persuasively argue their applicability to real time processing of dense signal environments.

Proposals must define a detailed path to an experimental demonstration of the memory module during the Phase I base period and a more notional plan for demonstrating the entire self-cued data thinning system before the end of the Phase II base period. These plans need to discuss how any components/functionality not existing today would be produced and with what technical risks.

Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by DoD 5220.22-M, National Industrial Security Program Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and ONR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material IAW DoD 5220.22-M during the advanced phases of this contract.

PHASE I: Demonstrate the feasibility of a way of providing a properly synchronized FIFO copy of 3 or more bit wide digital words at a flowing data rate above 20 GSps with time delays above 100 microseconds and a bit error rate below 10-12. Prepare a preliminary Phase II plan that discusses how to scale to wider words, higher data rate, and longer delays, plus comment on details like the impact of data packetization on the system performance. The Phase I option work, if exercised, should complete the production of the prototype memory module suitable for multi-bit 40 GSps ADCs and ideally demonstrate scaling to longer delays with no drop in BER, the bit error rate.

PHASE II: Develop and demonstrate a modular, adaptive, high bandwidth data thinning system. Functionalities that shall be demonstrated include: 1) proper recovery of a truncated data set containing the data that produced the self-cueing alert for a single < 10% duty cycle signal; 2) two differently processed signals from the same frequency sub-band within the same original data stream arriving into a data fusion processor with the proper relative timing; and 3) two differently processed signals from different frequency sub-bands within the same original data stream arriving into a data fusion processor with the proper relative timing. Progress on monitoring and controlling the absolute delivery- time delay and inserting the delayed data into the further back processors will be expected. Preference will be given to proposed efforts with little development work on the cue producing subsystem. The Phase II option effort, if exercised, shall incorporate the new delay module in some existing, probably classified signals analysis system and demonstrate the improved functionality. A proof that the improved systemís operation is independent of the signal waveform is be expected to be included.

It is probable that the work under this effort will become classified under Phase II (see Description section for details).

PHASE III DUAL USE APPLICATIONS: Full integration of the time delay unit into a working, classified ES system is predicted and tests of its performance advantages will follow. If the suggested server farm data links can be adapted for this use, the topic will be a dual use application, but the technology advancement driver will be dominated by the commercial side of the equation.

REFERENCES:

  1. MKS Newport. (n.d.). "Compact Time Delay Coils." https://www.newport.com/f/compact-time-delay-coil.
  2. Gupta, D.; Sarwana, S.; Kirichenko,D.; Dotsenko, V.; Lehmann, A. E.; Filippov, T. V.; Wong, W.-T.; Chang, S.-W.; Ravindran, P.; and Bardin, J. "Digital output data links from superconductor integrated circuits." IEEE Transactions on Applied Superconductivity, 29(5), 2019, pp. 1-8. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8686133.
  3. Stieber, S.; Dorsch, R.; and Haubelt, C. "Accurate Sample Time Reconstruction of Inertial FIFO Data." Sensors (Basel, Switzerland), 17(12), 2894, 2017. https://doi.org/10.3390/s17122894.
  4. Coffey, J. "Latency in optical fiber systems." COMMSCOPE, 2017. https://www.commscope.com/globalassets/digizuite/2799-latency-in-optical-fiber-systems-wp-111432-en.pdf.

KEYWORDS: First-in-first-out memory; FIFO; adaptive signals; Electro-magnetic support systems; time delay; digital data transmission; channel/time domain synchronization

** TOPIC NOTICE **

The Navy Topic above is an "unofficial" copy from the overall DoD 22.1 SBIR BAA. Please see the official DoD Topic website at rt.cto.mil/rtl-small-business-resources/sbir-sttr/ for any updates.

The DoD issued its 22.1 SBIR BAA pre-release on December 1, 2021, which opens to receive proposals on January 12, 2022, and closes February 10, 2022 (12:00pm est).

Direct Contact with Topic Authors: During the pre-release period (December 1, 2021 thru January 11, 2022) proposing firms have an opportunity to directly contact the Technical Point of Contact (TPOC) to ask technical questions about the specific BAA topic. Once DoD begins accepting proposals on January 12, 2022 no further direct contact between proposers and topic authors is allowed unless the Topic Author is responding to a question submitted during the Pre-release period.

SITIS Q&A System: After the pre-release period, proposers may submit written questions through SITIS (SBIR/STTR Interactive Topic Information System) at www.dodsbirsttr.mil/topics-app/, login and follow instructions. In SITIS, the questioner and respondent remain anonymous but all questions and answers are posted for general viewing.

Topics Search Engine: Visit the DoD Topic Search Tool at www.dodsbirsttr.mil/topics-app/ to find topics by keyword across all DoD Components participating in this BAA.

Help: If you have general questions about DoD SBIR program, please contact the DoD SBIR Help Desk via email at DoDSBIRSupport@reisystems.com

[ Return ]