Integrated Complementary Metal Oxide Semiconductor Nuclear Event Detector for System on a Chip Applications

Navy SBIR 22.1 - Topic N221-082
SSP - Strategic Systems Programs
Opens: January 12, 2022 - Closes: February 10, 2022 (12:00pm est)

N221-082 TITLE: Integrated Complementary Metal Oxide Semiconductor Nuclear Event Detector for System on a Chip Applications



The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop the techniques and circuitry needed to deploy a fully integrated Complementary Metal Oxide Semiconductor (CMOS) Nuclear Event Detector (NED). Additional objectives include the development of an all-digital interface to enable increased security and circumvention and recovery concepts of operations (CONOPS) flexibility.

DESCRIPTION: Nuclear Event Detectors are used in strategic systems to detect when a preset rate of prompt dose is deposited on the detector. Traditionally Nuclear Event Detectors are Hybrid type devices that incorporate a P-Type Intrinsic N-Type (PIN) semiconductor diode, which acts as a photocurrent collection volume which is then mated with other electronic components that appropriately bias the diode and detect when a set level of photo current is exceeded. These hybrid designs can be expensive and unwieldy – it would be highly desirable if a NED circuit could be fully incorporated into any CMOS Application Specific Integrated Circuit (ASIC). Additionally, an ASIC implementation would facilitate the inclusion of an all-digital threshold set point. This NED concept should be deployable into any CMOS Silicon on Oxide or bulk process. Since most commercial foundries do not allow modifications to the process flow, the expectation is that no modifications to the CMOS process recipe are allowed and adherence to process design rules must be followed. The challenge will be to fully integrate both the needed collection volume and related circuitry onto one CMOS die.

PHASE I: Develop a concept design for a fully integrated CMOS NED. Design concepts can be demonstrated in a Defense Microelectronics Activity (DMEA) certified trusted CMOS foundry. Simulation results utilizing industry standard Integrated Circuit Simulation Tools are expected to show concept feasibility including fidelity of the detection set point as well as the ability of the detection circuit itself to operate correctly in a prompt dose environment. A discussion of the technology volume limitations should be included in the Phase I study. Industry benchmarks of commercially available Nuclear Event Detectors should be used. For example, the HSN-3000 Nuclear Event Detector design benchmarks include [Ref 1]:

  • Dose Rate (operate-through): 1 x 1012 rad(Si)/sec
  • Total Dose Performance: 1 x 106 rad(Si)
  • Neutron Fluence: 5 x 1013 n/cm2
  • Approximate Detection Range: 2 x 105 - 2 x 107 rad(Si)/sec

The Phase I Option, if exercised, will include the initial design specifications, selected foundry, and capabilities description to build a prototype solution in Phase II.

PHASE II: The concept design and specifications from Phase I will be fully developed as a standalone Integrated Circuit (IC). Final circuit design viability will be demonstrated by simulations across process corners, the standard military temperature range, and modeled strategic radiation environments. The resulting design database will be used to fabricate a minimum of twenty-five (25) prototype die. All design schematics and layout files are part of the required deliverable. The prototypes should be delivered by the end of Phase II. These prototype parts will be tested and evaluated across environments by the SBIR sponsor [Ref 2].

PHASE III DUAL USE APPLICATIONS: The final version of the NED (in its standalone form) will be productized at the selected DMEA certified trusted foundry and made available to Strategic Programs. This final design should be suitable for either fabrication as a standalone NED or the design database could be leveraged by Strategic programs for the deployment into a larger SoC. Having the option to integrate the NED into program required ICs would reduce component costs as well as potentially provide additional detection coverage due to the increased number of locations in the weapon system the NED will reside.


  1. Data Device Corporation (DDC), HSN-3000 Device Features Web Page:
  2. Hash, G.L. and Schwank, J.R. et al: "Radiation characterization of a Monolithic nuclear event detector." Workshop record 1992, IEEE Radiation Effects Data Workshop,

KEYWORDS: NED; Nuclear Event Detector; collection volume; prompt dose; foundry; radiation environment


The Navy Topic above is an "unofficial" copy from the overall DoD 22.1 SBIR BAA. Please see the official DoD Topic website at for any updates.

The DoD issued its 22.1 SBIR BAA pre-release on December 1, 2021, which opens to receive proposals on January 12, 2022, and closes February 10, 2022 (12:00pm est).

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