Vertical Launch System High Speed Interface

Navy SBIR 24.1 - Topic N241-024
NAVSEA - Naval Sea Systems Command
Pre-release 11/29/23   Opens to accept proposals 1/03/24   Now Closes 2/21/24 12:00pm ET

N241-024 TITLE: Vertical Launch System High Speed Interface

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Integrated Sensing and Cyber

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Develop a high-speed interface within the MK41 Vertical Launch System (VLS) architecture.

DESCRIPTION: One of the biggest challenges VLS has with integration of new missiles and new capabilities relates to its low-speed interfaces and legacy technology of current platform hardware. The evolution of existing missiles and the advent of new missiles to meet an ever-changing threat have made upgrades to both system performance as well as reduced life cycle costs a necessary objective. Lifecycle cost reductions are needed in the redesign of the architecture where current legacy serial data exchange limits upgrades at both the launcher as well as the missile, and requires additional manhour expenditures for both maintenance as well as missile availability. Existing network interfaces are limited in speed and bandwidth, resulting in fenced performance limits affecting system availability and maintainability. Additionally, these interfaces, in their current configuration, establish a limit for optimization efforts between missile and weapon control system design and upgrade. A technology to redesign the interface between the Weapon Control System and the Missile to take advantage of High-Speed Ethernet capabilities will result in augmented magazine capacity, increased weapon availability, and reduced lifecycle costs.

Increased data rates would increase availability time for VLS in the fleet; for example, current Tomahawk upgrades can take hours per missile, which inhibits any launcher maintenance or action during that period. A key element to address these performance limitations is a redesign of the interface between the Aegis Combat System and the VLS Launch Control Unit, and the missile. The transition to a Gigabyte Ethernet architecture and definition of the Interface Control Document and Interface Design Specification requirements is sought to remedy these performance restrictions. Currently there are no commercial solutions to this issue.

A solution is needed to significantly enhance the performance of this interface while maintaining backward compatibility of existing data flows and timing. The solution must provide on-the-fly software upgrades and reduce downtime of VLS launch capabilities. Novel constructs that build upon current state-of-the-art network design will have the following specifications:

- Utilization of 802.3 1000BASELX (Gigabit) Ethernet Interface standard

- Interface of greater than 66 fiber ports (and extensible beyond this limit)

- Achieve benchmarks of 40MB in less than one minute and 400 MB in under 10 minutes, simultaneously, over 25% of the fiber ports

In-depth characterization and testing are critical for elucidating the mechanisms to achieve advanced data rates and digital assurance. Some critical considerations for any High-Speed Interface Processor (HSIP) would include design tradeoffs, Time Sensitive Networking protocol, development of a standard interface and compliance with Cybersecurity requirements. It is expected that the hardware developed can meet surface ship environmental requirements (e.g., MIL-DTL-901 Grade A shock, MIL-STD-167 Shipboard Vibration, 0-50C Ambient Temperature and MIL-STD-461 EMC). The awardee must propose adequate test protocols to demonstrate the suitability of the proposed technology to satisfy Navy requirements.

Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by 32 U.S.C. 2004.20 et seq., National Industrial Security Program Executive Agent and Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and NAVSEA in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material during the advanced phases of this contract IAW the National Industrial Security Program Operating Manual (NISPOM), which can be found at Title 32, Part 2004.20 of the Code of Federal Regulations. Reference: National Industrial Security Program Executive Agent and Operating Manual (NISP), 32 U.S.C. 2004.20 et seq. (1993). https://www.ecfr.gov/current/title-32/subtitle-B/chapter-XX/part-2004

PHASE I: Develop a concept for a common High-Speed Interface Processor (HSIP) to provide missile digital data that meets the parameters in the Description. Demonstrate that the concept can feasibly meet the requirements through analysis, modeling, and experimentation of materials of interest. The Phase I Option, if exercised, will include the initial design specifications and capabilities description to build a prototype solution in Phase II.

PHASE II: Develop and deliver notional full-scale prototype(s) that demonstrate functionality under the required service conditions including thermal stresses. Demonstrate the prototype performance through the required range of parameters given in the Description and as identified through Technical Interchange Meetings with the government.

It is probable that the work under this effort will be classified under Phase II (see Description section for details).

PHASE III DUAL USE APPLICATIONS: Support the Navy in transitioning the technology to Navy use in the MK41 VLS program. Support the manufacturing of the components employing the technology developed under this topic and assist in extensive qualification testing defined by the Navy program.

Potential commercial uses for high-speed interface processing performance improvements exist in the commercial industrial process, spacecraft, and aircraft industries.

REFERENCES:

  1. Galloway, Jeffrey. "Why Do We Need SERDES." ElectronicDesign, May 14 2020. https://www.electronicdesign.com/technologies/analog/article/21132088/why-do-we-need-serdes4
  2. Hopf, Daniel. "High-Speed Interfaces for High-Performance Computing" Continental_Corporation Holistic Engineering and Technologies, September 15, 2020. https://standards.ieee.org/wp-content/uploads/import/documents/other/eipatd-presentations/2020/D1-02-Hopf-HighSpeed-Interfaces-for-HighPerformance-Computing.pdf

KEYWORDS: Vertical Launch System; Gigabyte Ethernet; Time Sensitive Networking; VLS Launch Control Unit; Advanced Data Rates; Cybersecurity.


** TOPIC NOTICE **

The Navy Topic above is an "unofficial" copy from the Navy Topics in the DoD 24.1 SBIR BAA. Please see the official DoD Topic website at www.defensesbirsttr.mil/SBIR-STTR/Opportunities/#announcements for any updates.

The DoD issued its Navy 24.1 SBIR Topics pre-release on November 28, 2023 which opens to receive proposals on January 3, 2024, and now closes February 21, (12:00pm ET).

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